The present invention relates to patterning techniques in the fabrication of integrated circuit devices. In particular, the present invention relates to patterned etching techniques in the fabrication of integrated circuit devices. In particular, the present invention relates to methods of fabricating a patterned metal layer on top of a partially fabricated integrated circuit structure.
The conventional prior art of patterning integrated circuit structures uses a photoresist, i.e., a polymeric composition such that a developer solvent will selectively remove only the exposed (or, for different compositions, selectively only the unexposed) portions of the resist, leaving a patterned resist layer in place which provides a patterned mask for subsequent steps such as ion implementation, etching, or patterned deposition of materials by lift-off techniques (i.e., depositing a material over all and then removing the remaining portions of photoresist to leave the material only where the photoresist was not present).
However, this long established prior art patterning method has encountered substantial problems. First, difficulties arise in patterning the upper layers of the integrated circuit structure, where the patterns of the lower levels will provide substantial topography. Thus, a difficulty in metal patterning is typically the vertical excursion which can be substantial. That is, the metal will typically have to be patterned over a surface which is not flat but which may have a vertical variation of as much as a micron or two. This imposes great difficulties in focusing the optical pattern, since the vertical excursion may take portions of the surface out of the available depth of field. In the prior art, this difficulty has been avoided by using multi-layer resist processors. However, many multi-layer resist processes are difficult, unreliable, and more expensive.
Thus, it is an object of the present invention to provide an integrated circuit patterning method which can operate over non-planar topography at minimal expense and with minimal additional processing steps.
A further important limitation of prior art methods arises from pattern degradation due to reflection from the layer being patterned. For example, when a metal layer is being patterned, the places where the metal goes over a slope in the topography will induce lateral reflections of the incident exposing light. These may cause interference effects, or cause line width notching. In the prior art, use of dyed resists or anti-reflective coatings have been used in attempts to solve this problem. However, these efforts (where, e.g., an anti-reflective coating was deposited underneath the resist layer) still have their problems. The anti-reflective coating cannot achieve planarization, and thus the linewidth will still be modulated by the thickness variation in the top resist layer as it follows the topography. Alternatively, if the anti-reflective coating were deposited thickly enough to achieve planarization, then pattern degradation would occur as etching went through the patterned top resist layer through the (locally thick in some places) anti-reflective coating/planarization layer. No suitable materials are now known which can achieve anti-reflective absorption at a wavelength to which a top photoresist is sensitive, and provide planarization, and achieve good pattern transfer from the top layer.
Thus, it is an object of the present invention to suppress reflections from the substrate into the top resist layer, without degrading pattern transfer from the top resist layer.
It is a further object of the present invention to provide a method for integrated circuit patterning which both suppresses pattern degradation due to reflections from a substrate and also suppresses linewidth variation due to varying thickness of the top resist layer.
One major limitation in optical lithography is the resist linewidth variation across steps. This problem is more serious for a highly reflective substrate, and has been attributed to the non-uniform resist thickness near steps, which severely modulates the exposed energy coupled into the photoresist.
In the prior art, a bilayer resist process based on a conventional near-UV photoresist over PMMA structure has been used to improve the lithographic performance beyond the capability of a single layer resist process. See B. J. Lin, IEDM, San Francisco, CA, December 1982, which is hereby incorporated by reference. The thick PMMA layer is used to planarize the surface topography, so that a thin top imaging photoresist layer can be uniformly coated. This bilayer structure offers many attractive features. Better linewidth control can be obtained because of the planarization. The thin imaging layer also allows an improved resolution, a shorter exposure time, and a greater latitude for the depth of focus of the exposure system. High fidelity of pattern transfer from the top layer to the planarizing layer is achievable by deep UV flood exposure and then development of the bottom PMMA resist. Very sharp edge profiles in the PMMA layer result even if the top resist has an imperfect profile. This is because the deep UV light is absorbed strongly by the photoresist, and because very high selectivity of development between exposed and non-exposed PMMA is readily obtained.
However, there are still several drawbacks in implementing this bilayer resist process for production. See, C. H. Ting, I. Avigal, and B. C. Lu, Kodak Microelectronics Seminar, Interface '82, San Diego, CA, October, 1982, which is hereby incorporated by reference. For instance, there may exist a thin interface layer between the PMMA and the top resist, which can prevent uniform development of the PMMA. An extra stripping step before PMMA development either using dry descum or wet etch is required to give a more consistent clean development. The poor plasma etch resistance of PMMA, which is significantly worse than that of the Novolak-based resist materials, presents another disadvantage of the bilayer resist process. In addition, the nearly perfect transparency of PMMA in the near UV and visible wavelength ranges creates other problems in the bilayer resist structure. The standing wave effect is still present in the top layer photoresist, particularly if the substrate is highly reflective. Also, the light scattered from the wafer surface topography will degrade the pattern integrity of the top resist layer, and this problem is more severe when a thicker PMMA layer is used to accomplish better planarization; see, C. H. Ting, I. Avigal, and B. C. Lu, Kodak Microelectronics Seminar, Interface '82, San Diego, CA, October 1982, which is hereby incorporated by reference. It was reported by Bartlett, et al., that these reflective effects can be removed by adding absorbing dye into the PMMA; see K. Bartlett, G. Hillis, M. Chen, R. Trutna, and M. Watts, SPIE, Santa Clara, CA, March 1983, which is hereby incorporated by reference. However, the selection of the dye is very restricted, because the dye must be completely soluble into the PMMA, must be free from contamination, must strongly absorb the exposure light used for the top resist, must not degrade the alignment signal, and must not prevent
Recently, a spun-on anti-reflective (AR) layer coated between a conventional resist and substrate has been shown to be effective in reducing the adverse effects of light reflection from the substrate; see, Y. C. Lin, A. J. Purdes, S. A. Saller, and W. R. Hunter, IEDM, San Francisco, CA, December 1982, wich is hereby incorporated by reference. This process is by no means perfect because it still suffers from resist thickness non-uniformity near topographical steps.
In the present invention, a new multi-layer resist process in which a thin AR film is introduced between the thick bottom PMMA layer and the thin top photoresist of the bilayer resist process is reported. This novel resist process has the ultimate advantages of planarization as well as anti-reflectivity for the top imaging resist layer. Most of the above mentioned problems associated with both the conventional bilayer resist process and the AR coating in single layer resist process are completely eliminated. Significant improvement in the lithographic performance for a conventional reduction projection printer has been achieved with this new process.
The new multi-layer resist process, wherein a thin antireflective (AR) film is provided in addition to between the thick bottom PMMA layer and the top photoresist layer of the conventional bilayer resist process, has provided aluminum features of micron and submicron size over topography, using a conventional 10:1 reduction GCA DWS 4800 stepper to expose the top photoresist layer. Excellent linewidth control over steps is demonstrated. Both the standing wave effect in the top resist layer and the interference from the light scattered by the substrate topography are eliminated in this AR coating approach. The interface layer problem encountered in the original bilayer resist process does not appear in this new process. The plasma etch resistance of this new multi-layer resist process is improved by retaining the capping top photoresist layer, which also eliminates the delamination of the AR layer. This novel resist process provides a low-cost, reliable method for further extending the resolution capability of existing steppers to meet the needs of advanced product designs.
According to the present invention there is provided:
an integrated circuit patterning process comprising the steps of:
providing a substrate having partially formed integrated circuit structures on the top surface thereof;
depositing a first photoresist material over the top surface of said substrate, said first photoresist material being deposited to provide a substantially planar surface;
depositing an anti-reflective coating over said first photoresist material; and
depositing a second photoresist material over said anti-reflective material; and
exposing said second photoresist material to patterned optical illumination in a predetermined pattern.
According to the present invention there is provided:
an integrated circuit metallization process comprising the steps of:
providing a substrate having partially formed integrated circuit structures on the top surface thereof;
etching contact holes in predetermined locations;
depositing a thin film of a metal overall on said top surface;
depositing a first photoresist material over said metal film, said first photoresist material being deposited to provide a substantially planar surface;
depositing an anti-reflective coating over said firt photoresist material; and
depositing a second photoresist material over said anti-reflective material;
wherein said first photoresist material is photosensitive at a first wavelength to which said second photoresist material is opaque, PA1 and wherein said anti-reflective material is opaque at a second wvelength to which said second photoresist layer is sensitive;
exposing said second photoresist material to patterned optical illumination at said second wavelength in a predetermined pattern;
developing said second photoresist material, so that said second photoresist material is removed in areas determined by said predetermined pattern;
illuminating said first photoresist material at said first wavelength;
developing said first photoresist; and
exposing said integrated circuit structure to a predetermined metal etchant, whereby portions of said metal film exposed by said first photoresist layer are etched and portions of said metal film which are overlaid by remaining portions of said first photoresist layer are not substantially etched.